10.65-69.Hardware Implementation Of A Single Bit Error Code Correction.ANTON Constantin.IANA Gabriel.SERBAN Gh
نویسندگان
چکیده
In this paper is hamming code proposed implementing a structure for reconfigurable hardware for error correction bits on a line of communication. Algorithms for implementing the hamming code is made on a structure as simple and is aimed at the trials of code/decode the information to perform at a speed as much as possible, without the special hardware consumes resources. They are made functional simulations of implemented module and comparative results speed/resources occupied for various lengths of sequences.
منابع مشابه
FPGA Implementation of JPEG and JPEG2000-Based Dynamic Partial Reconfiguration on SOC for Remote Sensing Satellite On-Board Processing
This paper presents the design procedure and implementation results of a proposed hardware which performs different satellite Image compressions using FPGA Xilinx board. First, the method is described and then VHDL code is written and synthesized by ISE software of Xilinx Company. The results show that it is easy and useful to design, develop and implement the hardware image compressor using ne...
متن کاملHardware Implementation of Single Bit Error Correction and Double Bit Error Detection through Selective Bit Placement for Memory
Hamming codes are widely used for the single bit error correction double bit error detection (SEC-DED) which occurred during data transmission process. This paper presents an enhanced detection of double adjacent bit errors and correcting all possible single bit errors in Hamming codes through selective bit placement technique for memory application. Soft errors occur due to the radiation parti...
متن کاملImplementation of CDMA receiver using Recursive Digital Matched Filter
Code Division Multiple Access (CDMA) is a multiple access technique widely used in cellular and military communication systems. In Direct Sequence Spread Spectrum (DSSS) communications, data samples are embedded inside Pseudo Noise code (PN code) prior to transmission. Synchronization of this unique code with the incoming data samples forms an important step in data recovery. Single Dwell Seria...
متن کاملA Comparative Study of VHDL Implementation of FT-2D-cGA and FT-3D-cGA on Different Benchmarks (RESEARCH NOTE)
This paper presents the VHDL implementation of fault tolerant cellular genetic algorithm. The goal of paper is to harden the hardware implementation of the cGA against single error upset (SEU), when affecting the fitness registers in the target hardware. The proposed approach, consists of two phases; Error monitoring and error recovery. Using innovative connectivity between processing elements ...
متن کاملSingle Error Correcting Code Maximizes Memory System Efficiency
Jf eliable memory systems can be designed either by using highly reliable but expensive components or by employing inexpensive protective redundancy in terms of a single error correcting code that uses redundant check bits. The degree of reliability ean be increased if this protective redundancy matches the failure mode of the memory system, Presently, use of semiconductor memory is increasing ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2009